1. Field of the Invention
The present invention is related generally to host-adapter systems for information sharing between intelligent devices connected to a common data exchange bus such as a local area network (LAN) and more specifically to a method for rapidly accessing hardware request blocks stored in a memory either external or internal to a host adapter integrated circuit.
2. Description of Related Art
The Small Computer System Interface (SCSI) standard, which is specified by the American National Standards Institute (ANSI X3.131-1986, which is incorporated herein by reference in its entirety) of 1430 Broadway, New York, N.Y. 10018, is an example of an industry-recognized standard for a relatively complex local area network. Descriptions of the SCSI bus may be found for example in U.S. Pat. No. 4,864,291 "SCSI Converter" issued Sep. 5, 1989 to J. E. Korpi and in U.S. Pat. No. 4,905,184 "Address Control System for Segmented Buffer Memory" issued Feb. 27, 1990, to R. P. Giridhar, et al., which are incorporated herein by reference in their entirety.
A typical SCSI system 100 is illustrated in FIG. 1. A plurality of intelligent devices 120, 140, 141, 142 are coupled to SCSI bus 110 so that these devices can exchange information. The intelligent devices are (i) a first host system 120, whose internal structure is shown in detail, (ii) a second host system 140, whose internal structure is similar to that shown for system 120, (iii) a first disk drive unit (Target-A) 141, and (iv) a second disk drive unit (Target-B) 142.
Communications over SCSI bus 110 begin when one of devices 120, 140 initiates a data transfer. A typical data transfer operation has seven SCSI "phases": (1) ARBITRATE, (2) SELECT, (3) MESSAGE (out), (4) COMMAND, (5) DATA, (6) STATUS and (7) MESSAGE (in).
The operation of the SCSI phases for data transfer is well-known to those skilled in the art. Briefly, during the ARBITRATE phase, competing host systems 120 and 140 decide which system gains exclusive control of SCSI bus 110. During the SELECT phase, the winning host designates one of the other devices as a "target". After selection of the target, a command is issued from the host to specify the details of the data transfer, such as direction, length, and address of the data in the target. Data is transferred over the SCSI bus 110 either synchronously or asynchronously in blocks of, for example, 512 bytes each at a speed up to 20 megabytes (Mbytes) per second.
The host and target exchange handshakes for each byte of data transferred over the SCSI bus. When the target anticipates a time delay in the data stream, the chosen target disconnects (in the logic sense) from SCSI bus 110, and the winning host relinquishes control over SCSI bus 110. This leaves SCSI bus 110 in a Bus-Free state, permitting other SCSI transfer operations to take place over bus 110. The data transfer operations can be either single-threaded (one host-target pair is active at a time) or multi-threaded (one host initiates transfers with many targets concurrently).
While the advantages of SCSI are widely recognized, the implementation of the SCSI protocol can limit the performance of a SCSI bus. For example, if a SCSI host adapter is implemented in a single integrated circuit with an on-board memory for storing control blocks that define operations that are to be performed by the SCSI host adapter, the size of the on-board memory may limit the operation of the SCSI host adapter. For example, consider a SCSI host adapter integrated circuit, such as that disclosed in copending and commonly assigned U.S. patent application Ser. No. 07/964,532 entitled "Intelligent SCSI Bus Host Adapter Integrated Circuit," of Craig A. Stuber et al. filed on Oct. 16, 1992, which is incorporated wherein by reference in its entirety.
FIG. 2 is a block diagram of a host adapter integrated circuit 7770 that includes a SCSI module 230 for interfacing with a SCSI bus, a host interface module 210 for interfacing with a computer bus 226, a data first-in-first out memory circuit 260, a memory 240 and a sequencer 220. Memory 240 includes a sequencer memory 241, a scratch random access memory (RAM) 242, and a sequencer control block (SCB) memory 243. A detailed description of each of the modules and circuits in host adapter integrated circuit 7770 is given in co-pending and commonly assigned U.S. patent application Ser. No. 07/964,532 cited above and that description of each module and circuit is incorporated herein by reference. (FIG. 2 herein is the same as FIG. 4 in U.S. patent application Ser. No. 07/964,532, but the reference numerals have been changed for convenience.)
Briefly, sequencer 220 includes sequencer RAM 241 in memory 240, a RISC processor 222, and a sequencer register set 221. Scratch RAM area 242 in memory 240 is available for temporary storage of state information, e.g., in one embodiment a sequencer stack is maintained in scratch RAM 242.
Host adapter 7770 is controlled by a software driver 203, which includes an operating system specific module (OSM) 204 and a hardware interface module (HIM) 205 in main memory 227 of host computer system 200. OSM 204 knows nothing about the hardware in host adapter 7770 and communicates with both computer operating system 202 and HIM 205. HIM 205 communicates only with host adapter 7770 and OSM 204. OSM 204 builds a SCB and sends the SCB to HIM 205.
HIM 205 adds the SCB to a queue of SCBs maintained by HIM 205, and then HIM 205 checks for an available SCB slot in SCB array 243 onboard host adapter 7770. HIM 205 tracks four SCB slots "0" to "3" in SCB array 243 to determine the number of unused SCB slots. If a SCB slot is available, i.e. free, HIM 205 sets a bit PAUSE in a register HCNTRL in registers 211 thereby pausing sequencer 220. This prevents sequencer 220 and HIM 205 from colliding on a CIOBUS 250, thereby preventing a CIOBUS contention. HIM 205 loads an available SCB in SCB array 243 by transferring nineteen bytes into the available slot in SCB array 243 using a PIO data transfer, updates registers 211, in particular, places the page number, i.e. SCB slot, in queue-in FIFO 212 onboard host adapter 7770, and then unpauses sequencer 220.
Conversely, if a SCB slot is not available in SCB array 243, as indicated by the value of a register QINCNT in registers 211, the SCB remains queued in memory 227. When a SCB slot becomes available in SCB array 243, HIM 205 sends the oldest SCB in memory 227 to SCB array 243, as described above.
Each SCB in SCB array 243 includes a pointer to the SCSI command, a SCSI command length count, a pointer to a scatter/gather data transfer pointer list, a count of the number of elements in the scatter/gather list, the status returned by the target as well as temporary holding location and other statuses. Some of the values in the SCB are provided subsequently by HIM 205 or sequencer 220.
With the queued commands in SCB array 243, more than one target device may have commands open but disconnected. The four SCB slots are for general purpose SCBs and the SCBs in the four SCB slots may be used in any combination on either SCSI channel in SCSI module 230. To preserve the order of execution for any target/logic-unit-number (LUN) combination, the restriction is made that no more than two SCBs with the same target/channel/LUN identification can be loaded in SCB array 243. This restriction does not apply to tagged commands.
When sequencer 220 is not executing a SCSI command, sequencer 220 is in an idle loop and periodically scans the value of register QINCNT onboard host adapter 7770 to determine whether a new SCB has been loaded in SCB array 243. When a queued SCB is detected by reading register QINCNT, sequencer 220 loads SCB pointer register SCBPTR in registers 211 with the page number at the top of queue-in FIFO 212, which in turn decrements register QINCNT.
Since the address for every SCB is loaded into register SCBPTR and subsequently into the sequencer address circuitry, sequencer 220 must only specify an offset to obtain information from or write information to the active SCB.
The new SCB contains pointers to the SCSI command to be completed as well as the locations in host memory 227 to read or write data. Sequencer 220 attempts to execute the new SCB if it does not conflict with an already open SCB, i.e., the target/channel/LUN in the new SCB matches the target/channel/LUN in the SCB for an open command. Conversely, if the new SCB does conflict with an open command, the pointer for the SCB in register SCBPTR is written back to queue-in FIFO 212 and register QINCNT incremented.
Once a command is started, the target may disconnect. If a target does disconnect, sequencer 220 saves data pointers in the SCB for the command and marks the SCB as disconnected. In this case, sequencer 220 enters the idle loop and looks for the next SCB to execute. Notice that this is all done without the assistance of HIM driver 205 and all the necessary information is stored within host adapter 7770.
When reselection occurs, a search for a disconnected SCB with the same target/channel/LUN is made and when found, the disconnected SCB is continued. If two reselections, one on each channel, happen at the same time, a fairness algorithm is used to prevent one channel from being locked out.
In the case of tagged commands, the number of SCBs to the same target/channel/LUN may equal the space in SCB array 243. The commands are sent with the tag value generated by sequencer 220. Upon reselection, sequencer 220 matches target/channel/LUN/tag before completing the command.
When sequencer 220 is finished with the command, sequencer 220 moves the SCB pointer from register SCBPTR to queue-out FIFO 213 generates a hardware interrupt to microprocessor 225. Writing to register queue-out FIFO 213 increments the value in register QOUTCNT. Sequencer 220 then continues to execute any other SCBs that have been loaded.
In response to the hardware interrupt, host microprocessor 225 transfers control to OSM 204 which in turn calls the interrupt handler in HIM 205. HIM 205 queries interrupt status register INTSTAT in registers 211 to determine the cause of the hardware interrupt. HIM 205 notes that the SCSI command was completed and then queries queue-out FIFO 213 to determine which SCB was completed. HIM 205 transfers that information to OSM 204 which in turn notifies user application 201 and issues an end of interrupt signal EOI to microprocessor 225. OSM 204 then directs HIM to release the completed SCB. HIM 205 can read register queue-out FIFO 213 and register QOUTCNT until queue-out FIFO 213 is empty without pausing sequencer 220. Thus, HIM 205 can service commands that have completed without error without pausing sequencer 220. A SCB that completes normally does not need any status information copied back to the SCB in memory, and the next SCB can be copied directly on top of it.
Queuing the SCBs, and hence the SCSI commands, allows sequencer 220 to execute or suspend execution of a command at any point in the command sequence by updating the SCB to indicate the current completion status of the command.
Three parameters control SCB queuing by HIM 205:
______________________________________ 1) max.sub.-- nontag.sub.-- cmd = maximum number of active non-tagged SCBs per target ID. (Default is 2, other allowable value is 1.) 2) max.sub.-- tag.sub.-- cmd = maximum number of active tagged SCBs per target ID. (Default is 2, can range from 1 to 4.) 3) max.sub.-- total.sub.-- cmd = maximum number of total SCBs outstanding in sequencer 220. (Default and maximum is 4) ______________________________________
Sequencer 220 executes SCBs in the order that they are received in queue-in FIFO 212. If a non-tagged SCB is received for a target that is already active, sequencer 220 returns the SCB to queue-in FIFO 212. When a target disconnects, or a selection is in process, sequencer 220 scans queue-in FIFO 212 and other SCBs for any event that merits attention.
When an exception completion condition, e.g., selection timeout, parity error, occurs, sequencer 220 is paused due to either a SCSI or sequencer interrupt. For sequencer interrupts, the current SCB pointer determines which SCB caused the exception. For SCSI interrupts, HIM 205 may have to check all four internal SCBs in SCB array 243 to locate the source of the exception. If status, transfer information, etc. are needed, they can be copied from the internal SCB corresponding to the interrupt.
During the course of executing a SCB, there are three situations when SCBs in SCB array 243 must be located: i) prior to the execution of the SCB, to determine that the SCSI target is available to receive a new command; ii) after selection of the SCSI target is completed; and iii) after reconnection by the target.
In each of the three situations, SCB array 243 is searched to locate a SCB with a particular attribute, i.e., a) a target/LUN equal to the target/LUN in the SCB which is a candidate for starting; b) a SCB status of `waiting`; and c) a SCB status of `disconnected` and a target/LUN which is equal to the reconnecting target/LUN, respectively.
An SCB having one of these prescribed attributes is located by scanning SCB array 243 and examining each SCB in sequence. A serial scan is started at the top of array 243, and continues until either the objective SCB is found or the end of the array is reached. Two SCB attribute flag bits, `swait` and `sdiscon` are objects of SCB searches. Bit `swait` identifies a SCB as one waiting for a target selection to complete. Bit `Sdiscon` identifies a SCB as one for which the target has disconnected and not yet reconnected.
Since the maximum number of non-tagged queue SCBs resident in SCB array 243 at any given time for the same target/LUN is two, sequencer 220 does not start execution of a second SCB until the execution of the first SCB has completed to avoid receiving a `busy` error status from the target. Hence, before beginning execution of a SCB, sequencer 220 searches the SCB array 243 for another SCB with the same target/LUN and the bit `sdiscon` set. If such a SCB is found, commencement of SCB execution is postponed.
While selecting a target, sequencer 220 is in an "idle" loop or is responding to a reconnection. When selection is completed, sequencer 220 locates and retrieves the corresponding SCB. It does this by searching SCB array 243 for a SCB with the `swaiting` flag set.
Following reselection, when a target reconnects, the target provides sequencer 220 with its target and LUN addresses. Sequencer 220 searches SCB array 243 for a SCB with this target/LUN combination and bit `sdiscon` set. Since there is no ordering of SCBs in SCB array 243, the reconnecting SCB could be anywhere within SCB array 243. Again, sequencer 220 searches the entire SCB array 243, examining every SCB to retrieve the SCB for the reconnecting target.
Although serial scanning of the four active SCBs in internal SCB array 243 does not take an appreciable amount of time, the availability of only four active SCBs causes I/O bottlenecks in several situations. In addition, if the number of onboard active SCBs is increased, the serial scanning in the three situations outlined above as well as for SCSI interrupts may limit the performance of the host adapter integrated circuit. For operation in high capacity I/O environments, high speed operation coupled with a large number of active SCBs is required. In view of the limited number of onboard SCB slots and the serial scanning, host adapter integrated circuit 7770 and similar integrated circuit perform poorly in such an environment.